STM32L151V6H6TR(2013) 查看數據表（PDF） - STMicroelectronics
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STM32L151V6H6TR
(Rev.:2013)
(Rev.:2013)
STMicroelectronics
STM32L151V6H6TR Datasheet PDF : 121 Pages
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Electrical characteristics
STM32L151x6/8/B, STM32L152x6/8/B
6.3.15
Communications interfaces
I2C interface characteristics
The line I2C interface meets the requirements of the standard I2C communication protocol
with the following restrictions: SDA and SCL are not “true” open-drain I/O pins. When
configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled,
but is still present.
The I2C characteristics are described in Table 47. Refer also to Section 6.3.11: I/O current
injection characteristics for more details on the input/output alternate function characteristics
(SDA and SCL).
Table 47. I2C characteristics
Symbol
Parameter
Standard mode I2C(1) Fast mode I2C(1)(2)
Min
Max
Min
Max
Unit
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
th(STA)
tsu(STA)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
4.7
1.3
µs
4.0
0.6
250
100
0
0
900(3)
1000 20 + 0.1Cb 300
ns
300
300
4.0
0.6
µs
4.7
0.6
tsu(STO) Stop condition setup time
4.0
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
0.6
μs
1.3
μs
Cb
Capacitive load for each bus
line
400
400
pF
1. Guaranteed by design, not tested in production.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
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Doc ID 17659 Rev 8
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