STM32F100VC 查看數據表（PDF） - STMicroelectronics
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STM32F100VC Datasheet PDF : 98 Pages
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Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
5.3.15
Figure 27. I/O AC characteristics definition
90%
50%
10%
10%
50%
90%
EXT ERNAL
O UTP UT
ON 50pF
tr(I O)out
tr(I O)out
T
Maximum fr equency is achieved if (tr + tf) 2/3) T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 43).
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 9.
Table 46. NRST pin characteristics
Symbol
Parameter
Conditions Min Typ
Max Unit
VIL(NRST)(1) NRST Input low level voltage
VIH(NRST)(1) NRST Input high level voltage
–0.5
2
0.8
V
VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
200
mV
RPU
Weak pull-up equivalent resistor(2) VIN = VSS 30
40
VF(NRST)(1) NRST Input filtered pulse
VNF(NRST)(1) NRST Input not filtered pulse
300
50
kΩ
100
ns
ns
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
. the series resistance must be minimum (~10% order)
Figure 28. Recommended NRST pin protection
([WHUQDO
UHVHW FLUFXLW
9''
1567
538
)
,QWHUQDO UHVHW
)LOWHU
670)[
DLG
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 46. Otherwise the reset will not be taken into account by the device.
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Doc ID 15081 Rev 7
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