STM32F103VBT6 查看數據表（PDF） - STMicroelectronics

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STM32F103VBT6

Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces

STMicroelectronics 

STM32F103xx

Electrical characteristics

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 36 are derived from tests

performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions

summarized in Table 7.

Refer to Section 5.3.12: I/O port pin characteristics for more details on the input/output

alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 36. SPI characteristics(1)

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

tr(SCK)

tf(SCK)

tsu(NSS)(2)

th(NSS)(2)

tw(SCKH)(2)

tw(SCKL)(2)

SPI clock rise and fall

time

NSS setup time

NSS hold time

SCK high and low

time

tsu(MI) (2)

tsu(SI)(2)

Data input setup time

Master mode

Slave mode

Capacitive load: C=50 pF

Slave mode

Slave mode

Master mode, fPCLK= TBD,

presc = TBD

Master mode

Slave mode

Master mode

TBD

0

0

0

TBD

TBD

TBD

TBD

TBD

TBD

TBD

MHz

th(MI) (2)

th(SI)(2)

Data input hold time

Slave mode

Master mode, fPCLK= TBD

TBD

TBD(3)

Slave mode, fPCLK= TBD

TBD(3)

ns

ta(SO)(2)(4)

Data output access

time

Slave mode

Slave mode, fPCLK= TBD

TBD

TBD

TBD

TBD

tdis(SO)(2)(5)

Data output disable

time

Slave mode

TBD

TBD

Slave mode (after enable edge)

tv(SO) (2)(1) Data output valid time

fPCLK= TBD

tv(MO)(2)(1)

th(SO)(2)

th(MO)(2)

Data output valid time

Data output hold time

Master mode (after enable

edge)

fPCLK= TBD

Slave mode (after enable edge)

Master mode (after enable

edge)

TBD

TBD

TBD

TBD

TBD

TBD

TBD

1. TBD = to be determined.

2. Values based on design simulation and/or characterization results, and not tested in production.

3. Depends on fPCLK. For example, if fPCLK= 8MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns.

4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z

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