STM8AP6248UAX 查看數據表（PDF） - STMicroelectronics

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STM8AP6248UAX

Automotive 8-bit MCU, with up to32 Kbytes Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5V

STMicroelectronics 

Revision history

STM8AF61xx, STM8AF62xx

Table 52. Document revision history (continued)

Date

Revision

Changes

Modified references to reference manual, and Flash programming

manual in the whole document.

Added reference to AEC Q100 standard on cover page.

Renamed timer types as follows:

– Auto-reload timer to general purpose timer

– Multipurpose timer to advanced control timer

– System timer to basic timer

Introduced concept of medium density Flash program memory.

Updated timer names in Figure 1: STM8A block diagram.

Added TMU brief description in Section 5.4: Flash program and data

EEPROM, and updated TMU_MAXATT description in Table 18:

Option byte description.

31-Jan-2011

Updated clock sources in clock controller features (Section 5.5.1).

Changed 16MHZTRIM0 to HSITRIM bit in Section : User trimming.

Added Table 4: Peripheral clock gating bits in Section 5.5.6.

Updated Section 5.6: Low-power operating modes.

Added calibration using TIM3 in Section 5.7.2: Auto-wakeup counter.

Added Table 7: ADC naming and Table 8: Communication peripheral

5

naming correspondence.

Added Note 1 related AIN12 pin in Section 5.8: Analog-to-digital

converter (ADC)and Table 10: STM8AF61xx/62xx (32 Kbytes)

microcontroller pin description.

Updated SPI data rate to 10 Mbit/s or fMASTER/2 in Section 5.9.1:

Serial peripheral interface (SPI).

Added reset state in Table 9: Legend/abbreviation.

Table 10: STM8AF61xx/62xx (32 Kbytes) microcontroller pin

description: added Note 7 related to PD1/SWIM, modified Note 6,

corrected wpu input for PE1 and PE2, and renamed TIMn_CCx and

TIMn_NCCx to TIMn_CHx and TIMn_CHxN, respectively.

Section 7.2: Register map:

Replaced tables describing register maps and reset values for non-

volatile memory, global configuration, reset status, clock controller,

interrupt controller, timers, communication interfaces, and ADC, by

Table 13: General hardware register map.

Added Note 1 for Px_IDR registers in Table 12: I/O port hardware

register map. Updated register reset values for Px_IDR registers.

Added SWIM and debug module register map.

86/89

Doc ID 14952 Rev 6

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