COM20022I3V-HT 查看數據表（PDF） - SMSC -> Microchip
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COM20022I3V-HT Datasheet PDF : 73 Pages
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
XTAL1
4.0V
t1
t2
1.0V
t3
50% of VDD
Parameter
t1
Input Clock High Time
t2
Input Clock Low Time
t3
Input Clock Period*
t4
Input Clock Frequency*
t5
Frequency Accuracy*
min typ max units
20
nS
20
nS
50
100 nS
10
20 MHz
-200
200 ppm
Note*: Input clock frequency must be 20 MHz (+- 100ppm or better) to use the internal Clock Multiplier.
t4 and t5 are applied to crystal oscillaton.
Figure 8.15 - TTL Input Timing on XTAL1 Pin
t1
nRESET
nINTR
t2
Parameter
min typ
t1
nRESET Pulse Width***
t2
nINTR High to Next nINTR Low EF = 0
EF = 1
5TXTL*
TDR**/2
4TXTL*
Note*: TXTL is period of external XTAL oscillation frequency.
Note**: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after VDD was over 4.5V.
Figure 8.16 - Reset and Interrupt Timing
max units
SMSC COM20022I 3.3V Rev.C
Page 67
DATASHEET
Revision 03-08-07
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