R5F1036AASP-W0 查看數據表（PDF） - Renesas Electronics

零件编号

产品描述 (功能)

生产厂家

R5F1036AASP-W0

RENESAS MCU True Low Power Platform (as low as 63 μA/MHz), 1.8V to 5.5V operation, 2 to 16 Kbyte Flash, 31 DMIPS at 24MHz, for General Purpose Applications

Renesas Electronics 

RL78/G12

2. ELECTRICAL SPECIFICATIONS (A, D: TA = −40 to +85°C)

<R> (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock

output) (3/3)

(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed LS (low-speed

Unit

main) Mode

main) Mode

MIN. MAX. MIN. MAX.

SIp setup time

tSIK1

4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

44

110

ns

(to SCKp↓) Note 1

Cb = 30 pF, Rb = 1.4 kΩ

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

44

110

ns

Cb = 30 pF, Rb = 2.7 kΩ

1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,

110

110

ns

Cb = 30 pF, Rb = 5.5 kΩ

SIp hold time

tKSI1

4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

19

19

ns

(from SCKp↓) Note 1

Cb = 30 pF, Rb = 1.4 kΩ

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

19

19

ns

Cb = 30 pF, Rb = 2.7 kΩ

1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,

19

19

ns

Cb = 30 pF, Rb = 5.5 kΩ

Delay time from

SCKp↑ to

SOp output Note 1

tKSO1

4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 kΩ

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 kΩ

25

25

ns

25

25

ns

1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 kΩ

25

25

ns

<R> Notes 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

2. Use it with VDD ≥ Vb.

<R> Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode

for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode

register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.

2. CSI01 and CSI11 cannot communicate at different potential.

Remarks 1.

2.

Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)

load capacitance, Vb [V]: Communication line voltage

p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)

CSI mode connection diagram (during communication at different potential)

<Master>

SCKp

RL78

microcontroller

SIp

SOp

Vb

Rb

Vb

Rb

SCK

SO User's device

SI

R01DS0193EJ0200 Rev.2.00

Sep 06, 2013

Page 45 of 106

Share Link: