R5F1036ADSP-X0 查看數據表（PDF） - Renesas Electronics

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R5F1036ADSP-X0

RENESAS MCU True Low Power Platform (as low as 63 μA/MHz), 1.8V to 5.5V operation, 2 to 16 Kbyte Flash, 31 DMIPS at 24MHz, for General Purpose Applications

Renesas Electronics 

RL78/G12

2. ELECTRICAL SPECIFICATIONS (A, D: TA = −40 to +85°C)

2.4 AC Characteristics

(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

<R>

Items

Symbol

Conditions

Instruction cycle (minimum TCY

instruction execution time)

Main system

clock (fMAIN)

operation

HS (High-

speed main)

mode

2.7 V ≤ VDD ≤ 5.5 V

2.4 V ≤ VDD < 2.7 V

LS (Low-

speed main)

mode

1.8 V ≤ VDD ≤ 5.5 V

During self

programming

HS (High-

speed main)

mode

2.7 V ≤ VDD ≤ 5.5 V

2.4 V ≤ VDD < 2.7 V

LS (Low-

speed main)

mode

1.8 V ≤ VDD ≤ 5.5 V

External main system clock fEX

frequency

2.7 V ≤ VDD ≤ 5.5 V

2.4 V ≤ VDD < 2.7 V

1.8 V ≤ VDD < 2.4 V

External main system clock

input high-level width, low-

level width

tEXH, tEXL

2.7 V ≤ VDD ≤ 5.5 V

2.4 V ≤ VDD < 2.7 V

1.8 V ≤ VDD < 2.4 V

TI00 to TI07 input high-level tTIH, tTIL

width, low-level width

TO00 to TO07 output

frequency

PCLBUZ0, or PCLBUZ1

output frequency

INTP0 to INTP5 input high-

level width, low-level width

KR0 to KR9 input available

width

RESET low-level width

fTO

fPCL

tINTH, tINTL

tKR

tRSL

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

1.8 V ≤ VDD < 2.7 V

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

1.8 V ≤ VDD < 2.7 V

MIN.

0.04167

0.0625

0.125

0.04167

0.0625

0.125

1.0

1.0

1.0

24

30

60

1/fMCK +

10

1

250

10

TYP.

MAX.

1

1

1

1

1

1

20.0

16.0

8.0

12

8

4

16

8

4

Unit

μs

μs

μs

μs

μs

μs

MHz

MHz

MHz

ns

ns

ns

ns

MHz

MHz

MHz

MHz

MHz

MHz

μs

ns

μs

Remark

fMCK: Timer array unit operation clock frequency

(Operation clock to be set by the timer clock select register 0 (TPS0) and the CKS0n bit of timer mode

register 0n (TMR0n). n: Channel number (n = 0 to 7))

R01DS0193EJ0200 Rev.2.00

Sep 06, 2013

Page 28 of 106

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