CS42L56 查看數據表（PDF） - Cirrus Logic

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CS42L56

Ultralow Power, Stereo Codec with Class H Headphone Amp

Cirrus Logic 

6.4.2

Line Power Control

Configures how the HPDETECT pin, 29, controls the power for the line amplifier.

PDN_LINx[1:0]

00

01

10

11

Line Status

Line channel is ON when the HPDETECT pin, is LO.

Line channel is OFF when the HPDETECT pin, is HI.

Line channel is ON when the HPDETECT pin, is HI.

Line channel is OFF when the HPDETECT pin, is LO.

Line channel is always ON.

Line channel is always OFF.

CS42L56

6.5 Clocking Control 1 (Address 05h)

7

Reserved

6

5

4

M/S

INV_SCLK

SCK=MCK1

3

SCK=MCK0

2

MKPREDIV

1

MCLKDIV2

0

MCLKDIS

6.5.1

Master/Slave Mode

Configures the serial port I/O clocking.

M/S

0

1

Application:

Serial Port Clocks

Slave (Input ONLY)

Master (Output ONLY)

“Serial Port Clocking” on page 47

6.5.2

SCLK Polarity

Configures the polarity of the SCLK signal.

INV_SCLK

0

1

SCLK Polarity

Not Inverted

Inverted

6.5.3

SCLK Equals MCLK

Configures the SCLK signal source and speed for master mode.

SCK=MCK[1:0]

00

01

10

11

Output SCLK

Re-timed, bursted signal with minimal speed needed to clock the required data samples

Reserved

MCLK signal after the MCLK divide by 2 (MCLKDIV2) circuit

MCLK signal before the MCLK divide by 2 (MCLKDIV2) circuit

Note: The SCK=MCK[1:0] bits must be set to “00” when the device is in slave mode.

6.5.4

MCLK Pre-Divide

Configures a divide of the input MCLK prior to all internal circuitry.

MKPREDIV

0

1

Application:

MCLK signal into CODEC

No divide

Divided by 2

“Serial Port Clocking” on page 47

DS851F2

59

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