CS42L56 查看數據表（PDF） - Cirrus Logic
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CS42L56 Datasheet PDF : 92 Pages
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4.2.1
CS42L56
Pseudo-differential Inputs
The CS42L56 implements a pseudo-differential input stage. The AINxREF inputs are intended to be used
as a pseudo-differential reference signal. This feature provides common mode noise rejection with single-
ended signals. Figure 14 shows a basic diagram outlining the internal implementation of the pseudo-dif-
ferential input stage, including a recommended stereo pseudo-differential input topology. If pseudo-differ-
ential input functionality is not required, the AINxREF pin should be AC-coupled to GND.
V=?
VCM
Signal+
DC-Block
xIN
xREF
Parallel PCB
traces from
signal source
VCM
Common-Mode Cancellation,
Invert, and Gain
VCM
-
+
Anti-
Aliasing
Filter
ADC
Digital
Full Scale
VA
R-
VQ
VCM +
R
AGND
VCM
AFILTx
Figure 14. Stereo Pseudo-Differential Input
It should be noted that the AINxREF inputs are intended to be used solely to provide a low-level, pseudo-
differential reference signal for the internal input amplifiers when in pseudo-differential mode. Using the
analog input pins in a fully differential configuration by providing a large signal on the AINxREF pin is not
recommended. The output of the PGA will clip if the voltage difference between AINxx and AINxREF ex-
ceeds the full-scale voltage specification (See Note 10 on page 17).
4.2.2
Large-scale Inputs
The CS42L56 allows the user to input signals that would be larger than the ADC full-scale input voltage
by using the PGA to attenuate the signal prior to going to the ADC. Table 1 shows the PGA gain setting
needed to stay under the maximum ADC input voltage.
Supply Voltage
(V)
1.8
2.5
PGA Gain Setting
(dB)
0.0
-0.5
-1.0
-1.5
0.0
-0.5
-1.0
-1.5
Maximum Input Voltage
(mVRMS)
(VPP)
509
1.44
539
1.52
571
1.62
604
1.71
707
2.00
748
2.12
793
2.24
840
2.38
Table 1. Input Voltage PGA Settings
32
DS851F2
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