CS42L56 查看數據表（PDF） - Cirrus Logic
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CS42L56 Datasheet PDF : 92 Pages
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SWITCHING CHARACTERISTICS - SPI CONTROL PORT
Inputs: Logic 0 = GND = AGND, Logic 1 = VL, SDA CL = 30 pF.
Parameter
Symbol
Min
CCLK Clock Frequency
RESET Rising Edge to CS Falling
CS Falling to CCLK Edge
CS High Time Between Transmissions
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
fsck
0
tsrs
20
tcss
20
tcsh
1.0
tscl
66
tsch
66
tdsu
40
(Note 24)
tdh
15
(Note 25)
tr2
-
(Note 25)
tf2
-
Notes:
24. Data must be held for sufficient time to bridge the transition time of CCLK.
25. For fsck <1 MHz.
RESET
tsrs
CS42L56
Max
6.0
-
-
-
-
-
-
-
100
100
Units
MHz
ns
ns
s
ns
ns
ns
ns
ns
ns
CS
tcss
tsch
tscl
tcsh
tr2
CCLK
tf2
tdsu
tdh
CDIN
Figure 11. Control Port Timing - SPI Format
24
DS851F2
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