AT91SAM7S512 查看數據表（PDF） - Atmel Corporation

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AT91SAM7S512

AT91SAM ARM-based Flash MCU

Atmel Corporation 

Problem Fix/Workaround

Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and

the others differ from 1 if NCPHA = 0 and CPOL = 1.

If all chip selects are configured with Baudrate = 1, the issue does not appear.

40.25.5 Synchronous Serial Controller (SSC)

40.25.5.1 SSC: Periodic Transmission Limitations in Master Mode

If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.

Problem Fix/Workaround

None.

40.25.5.2 SSC: Transmitter Limitations in Slave Mode

If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge

(rising or falling) of synchro has a Start Delay equal to zero.

Problem Fix/Workaround

None.

40.25.5.3 SSC: Transmitter Limitations in Slave Mode

If TK is programmed as an input and TF is programmed as an output and requested to be set to low/high during

data emission, the Frame Synchro signal is generated one bit clock period after the data start and one data bit is

lost. This problem does not exist when generating a periodic synchro.

Problem Fix/Workaround

The data need to be delayed for one bit clock period with an external assembly.

In the following schematic, TD, TK and NRST are SAM7S signals, TXD is the delayed data to connect to the

device.

SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

750

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