ISPXPLD5256MX 查看數據表（PDF） - Lattice Semiconductor
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ISPXPLD5256MX
Lattice Semiconductor
ISPXPLD5256MX Datasheet PDF : 92 Pages
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
tPWH
Input clock, high time
80% to 80%
tPWL
Input clock, low time
20% to 20%
tR, tF
Input Clock, rise and fall time
20% to 80%
tINSTB
Input clock stability, cycle to cycle (peak)
fMDIVIN
M Divider input, frequency range
fMDIVOUT
M Divider output, frequency range
fNDIVIN
N Divider input, frequency range
fNDIVOUT
N Divider output, frequency range
fVDIVIN
V Divider input, frequency range
fVDIVOUT
V Divider output, frequency range
tOUTDUTY
Output clock, duty cycle
Clean reference.
tJIT(CC)
Output clock, cycle to cycle jitter (peak)
10 MHz < fMDIVOUT < 20 MHz or
100MHz < fVDIVIN < 160 MHz1
Clean reference.
20 MHz < fMDIVOUT < 320 MHz and
160MHz < fVDIVIN < 320 MHz1
Clean reference.
TJIT(PERIOD)2 Output clock, period jitter (peak)
10 MHz < fMDIVOUT < 20 MHz or
100MHz < fVDIVIN < 160 MHz1
Clean reference.
20 MHz < fMDIVOUT < 320 MHz and
160MHz < fVDIVIN < 320 MHz1
tCLK_OUT_DLY Input clock to CLK_OUT delay
Internal feedback
tPHASE
Input clock to external feedback delta
External feedback
tLOCK
Time to acquire phase lock after input stable
tPLL_DELAY
Delay increment (Lead/Lag)
Typical = +/- 250ps
tRANGE
Total output delay range (lead/lag)
tPLL_RSTW
Minimum reset pulse width
tCLK_IN3
Global clock input delay
tPLL_SEC_DELA Secondary PLL output delay (tPLL_DELAY)
Y
1. This condition assures that the output phase jitter will remain within specification.
2. Accumulated jitter measured over 10,000 waveform samples.
3. Internal timing for reference only.
Min Max
1.2
—
1.2
—
—
3.0
— +/- 250
10
320
10
320
10
320
10
320
100 400
10
320
40
60
— +/- 250
— +/- 150
— +/- 300
— +/- 150
—
3.0
—
600
—
25
+/- 120 +/- 550
+/- 0.84 +/- 3.85
—
1.8
—
1.0
—
1.5
Units
ns
ns
ns
ps
MHz
MHz
MHz
MHz
MHz
MHz
%
ps
ps
ps
ps
ns
ps
us
ps
ns
ns
ns
ns
43
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