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STAP16DPPS05XTTR(2015) 查看數據表(PDF) - STMicroelectronics

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STAP16DPPS05XTTR Datasheet PDF : 33 Pages
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Error detection mode functionality
7
Error detection mode functionality
STAP16DPPS05
7.1
Phase one: entering error detection mode
From the “normal mode” condition the device can switch to “error mode” by a logic
sequence on the OE/DM2 and LE/DM1 pins, as shown in the following table and diagram:
Table 13. Entering error detection mode - truth table
CLK
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
H
L
Figure 18. Entering error detection mode - timing diagram
CLK
OE/DM2
LE/DM1
AM13668v1
After these five CLK cycles, the device goes into the “error detection mode” and at the 6th
rising edge of the CLK, the SDI data are ready for sampling.
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DocID024306 Rev 6

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