CS5490-ISZR 查看數據表（PDF） - Cirrus Logic

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CS5490-ISZR

Two Channel Energy Measurement IC

Cirrus Logic 

CS5490

6.6.10 Phase Sequence Detection and Control (PSDC) – Page 0, Address 48

23

DONE

15

-

7

-

22

PSCNT[6]

14

-

6

-

21

PSCNT[5]

13

-

5

DIR

20

PSCNT[4]

12

-

4

CODE[4]

19

PSCNT[3]

11

-

3

CODE[3]

18

PSCNT[2]

10

-

2

CODE[2]

17

PSCNT[1]

9

-

1

CODE[1]

16

PSCNT[0]

8

-

0

CODE[0]

Default = 0x00 0000

DONE

Indicates valid count values reside in PSCNT[6:0].

0 = Invalid values in PSCNT[6:0]. (Default)

1 = Valid values in PSCNT[6:0].

PSCNT[6:0]

Registers the number of OWR samples from the start time to the time when the next

zero crossing is detected.

[15:6]

Reserved.

DIR

Set the zero-crossing edge direction which will stop PSCNT count.

0 = Stop count at negative to positive zero-crossing - Rising Edge. (Default)

1 = Stop count at positive to negative zero-crossing - Falling Edge.

CODE[4:0]

Write 10110 to this location to enable the phase sequence detection.

6.6.11 Checksum of Critical Registers (RegChk) – Page 16, Address 1

MSB

LSB

223

222

221

220

219

218

217

216

.....

26

25

24

23

22

21

20

Default = 0x00 0000

This register contains the checksum of critical registers.

DS982F2

37

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