CS5490-ISZR 查看數據表（PDF） - Cirrus Logic

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CS5490-ISZR

Two Channel Energy Measurement IC

Cirrus Logic 

CS5490

5. FUNCTIONAL DESCRIPTION

5.1 Power-on Reset (POR)

The CS5490 has an internal power supply supervisor

circuit that monitors the VDDA and VDDD power

supplies and provides the master reset to the chip. If

any of these voltages are in the reset range, the master

reset is triggered.

Both the analog and the digital supply have their own

POR circuit. During power-up, both supplies have to be

above the rising threshold for the master reset to be

de-asserted.

Each POR is divided into 2 blocks: rough and fine.

Rough POR triggers the fine POR. Rough POR

depends only on the supply voltage. The trip point for

the fine POR is dependent on bandgap voltage for

precise control.

The POR circuit also acts as a brownout detect. The fine

POR detects supply drops and asserts the master reset.

The rough and fine PORs have hysteresis in their rise

and fall thresholds which prevents the reset signal from

chattering.

The following plot shows the POR outputs for each of

the power supplies. The POR_Fine_VDDA and

POR_Fine_VDDD signals are AND-ed to form the

actual power-on reset signal to the digital circuity. The

digital circuitry, in turn, holds the master reset signal for

130ms and then de-asserts the master reset.

Vth2

VDDA

Vth1

Vth5

Vth6

POR_Rough_VDDA

POR_Fine_VDDA

VDDD

Vth4

Vth3

Vth7

Vth8

Table 1. POR Thresholds

Typical POR

Threshold

Rising

Falling

VDDA

Rough

Fine

Vth1 = 2.34V

Vth2 = 2.77V

Vth6 = 2.06V

Vth5 = 2.59V

VDDD

Rough

Fine

Vth3 = 1.20V

Vth4 = 1.51V

Vth8 = 1.06V

Vth7 = 1.42V

5.2 Power Saving Modes

Power Saving modes for CS5490 are accessed through

the Host Instruction Commands (see 6.1 Host

Commands on page 24).

• Standby: Powers down all the ADCs, rough buffer,

and the temperature sensor. Standby mode disables

the system time calculations. Use the wake-up

command to come out of standby mode.

• Wake-up: Clears the ADC power-down bits and

starts the system time calculations.

After any of these commands are completed, the DRDY

bit is set in the Status0 register.

5.3 Zero-crossing Detection

Zero-crossing detection logic is implemented in

CS5490. A low-pass filter can be enabled by setting

ZX_LPF bit in register Config2. The low-pass filter has

a cut-off frequency of 80Hz. It is used to eliminate any

harmonics and to help the zero-crossing detection on

the 50Hz or 60Hz fundamental component. The

zero-crossing level registers are used to set the

minimum threshold over which the channel peak has to

exceed in order for the zero-crossing detection logic to

function. There are two separate zero-crossing level

registers: VZXLEVEL is the threshold for the voltage

channels, and IZXLEVEL is the threshold for the current

channels.

POR_Rough_VDDD

POR_Fine_VDDD

POR_Fine_VDDA

POR_Fine_VDDD

Master Reset

130 ms

Figure 8. Power-on Reset Timing

18

DS982F2

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