STM32F215IEH6 查看數據表（PDF） - STMicroelectronics

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STM32F215IEH6

ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

STM32F21xxx

Electrical characteristics

Synchronous waveforms and timings

Figure 57 through Figure 60 represent synchronous waveforms and Table 74 through

Table 76 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

● BurstAccessMode = FSMC_BurstAccessMode_Enable;

● MemoryType = FSMC_MemoryType_CRAM;

● WriteBurst = FSMC_WriteBurst_Enable;

● CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual)

● DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

In all timing tables, the THCLK is the HCLK clock period.

Figure 57. Synchronous multiplexed NOR/PSRAM read timings

tw(CLK)

tw(CLK)

BUSTURN = 0

FSMC_CLK

FSMC_NEx

td(CLKL-NADVL)

FSMC_NADV

FSMC_A[25:16]

Data latency = 0

td(CLKL-NExL)

td(CLKL-NADVH)

td(CLKL-AV)

t d(CLKL-NExH)

td(CLKL-AIV)

td(CLKH-NOEL) td(CLKL-NOEH)

FSMC_NOE

td(CLKL-ADV)

FSMC_AD[15:0]

td(CLKL-ADIV)

tsu(ADV-CLKH)

AD[15:0]

tsu(NWAITV-CLKH)

th(CLKH-ADV)

tsu(ADV-CLKH)

D1

D2

th(CLKH-ADV)

th(CLKH-NWAITV)

FSMC_NWAIT

(WAITCFG = 1b, WAITPOL + 0b)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

ai14893h

Doc ID 17050 Rev 8

127/173

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