MPC5200BDS 查看數據表（PDF） - Freescale Semiconductor

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MPC5200BDS

SDRAM/DDR Memory Controller

Freescale Semiconductor 

DMARQ

( device )

DMARQ

( host )

STOP

( host )

HDMARDY

( host )

t RP

t SR

t RFS

DSTROBE

( device )

DD [ 0 : 15 ]

( device )

Figure 18. Timing Diagram—Host Pausing an Ultra DMA Data In Burst

DMARQ

(device)

DMACK

(host)

STOP

(host)

HDMARDY

(host)

t SS

DSTROBE

(device)

DD [ 0 : 15 ]

tLI

tLI

t ZAH

t AZ

t LI

t MLI

t ACK

t ACK

t IORDYZ

t DVS

CRC

t DVH

DA0, DA1, DA2,

t ACK

CS [ 0 : 1 ]

Figure 19. Timing Diagram—Drive Terminating Ultra DMA Data In Burst

MPC5200B Data Sheet, Rev. 4

34

Freescale Semiconductor

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