CL-PS7110 查看數據表（PDF） - Cirrus Logic

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CL-PS7110

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7110

Low-Power System-on-a-Chip

3.2.3 PCDR — Port C Data Register

Values written to this 8-bit read/write register are output on the Port C pins if the corresponding data direc-

tion bits are set low (port output). Values read from this register reflect the external state of Port C, not

necessarily the value written to it. All bits are cleared by a system reset.

3.2.4 PDDR — Port D Data Register

Values written to this 8-bit read/write register are output on the Port D pins if the corresponding data direc-

tion bits are set low (port output). Values read from this register reflect the external state of Port C, not

necessarily the value written to it. All bits are cleared by a system reset.

3.2.5 PADDR — Port A Data Direction Register

Bits set in this 8-bit read/write register select the corresponding pin in Port A to become an output; clearing

a bit sets the pin to input. All bits are cleared by a system reset so that Port A is input by default.

3.2.6 PBDDR — Port B Data Direction Register

Bits set in this 8-bit read/write register select the corresponding pin in Port B to become an output; clearing

a bit sets the pin to input. All bits are cleared by a system reset so that Port A is input by default.

3.2.7 PCDDR — Port C Data Direction Register

Bits cleared in this 8-bit read/write register select the corresponding pin in Port C to become an output;

setting a bit sets the pin to input. All bits are cleared by a system reset so that Port C is output by default.

3.2.8 PDDDR — Port D Data Direction Register

Bits cleared in this 8-bit read/write register select the corresponding pin in Port D to become an output;

setting a bit sets the pin to input. All bits are cleared by a system reset so that Port D is output by default.

3.2.9 PEDR — Port E Data Register

Values written to this 4-bit read/write register are output on Port E pins if the corresponding data direction

bits are set high (port output). Values read from this register reflect the external state of Port E, not nec-

essarily the value written to it. All bits are cleared by a system reset.

3.2.10 PEDDR — Port E Data Direction Register

Bits set in this 4-bit read/write register select the corresponding pin in Port E to become an output; clearing

a bit sets the pin to input. All bits are cleared by a system reset so that Port E is input by default.

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PROGRAMMING INTERFACE

May 1997

DATA BOOK v1.5

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