CS89712-CB 查看數據表（PDF） - Cirrus Logic

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CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

same way as the timer counters, but is 32 bits wide.

The RTC is always clocked at 1 Hz, generated from

the 32.768 kHz oscillator. It also contains a 32-bit

output match register, this can be programmed to

generate an interrupt when the count in the RTC

matches a specific value written to this register.

The RTC can only be reset by an nPOR cold reset.

Because the RTC data register is updated from the

1 Hz clock derived from the 32 kHz source, which

is asynchronous to the main memory system clock,

the data register should always be read twice to en-

sure a valid and stable reading. This also applies

when reading back the RTCDIV field of the

SYSCON1 register, which reflects the status of the

six LSBs of the RTC counter.

2.20.1 RTC Interface Characteristics

When connecting a crystal to the RTC interface

pins (i.e., RTCIN and RTCOUT), the crystal and

circuit should conform to the following:

• The 32.768 kHz frequency should be created

by the crystals fundamental tone (i.e., it should

be a fundamental mode crystal)

• A start-up resistor is not necessary, since one is

provided internally.

• Start-up loading capacitors may be placed on

each side of the external crystal and ground.

Their value should be in the range of 10 pF.

However, their values should be selected based

upon the crystal specifications. The total sum of

the capacitance of the traces between the

CS89712’s clock pins, the capacitors, and the

crystal leads should be subtracted from the

crystal’s specifications when determining the

values for the loading capacitors.

• The crystal should have a maximum 5 ppm fre-

quency drift over the chip’s operating tempera-

ture range.

• The voltage for the crystal must be 2.5 V + 0.2 V.

Alternatively, a digital clock source can be used to

drive the RTCIN pin of the CS89712. With this ap-

proach, the voltage levels of the clock source

should match that of the VDD supply for the

CS89712’s pads (i.e., the supply voltage level used

to drive all of the non-VDD core pins on the

CS89712) (i.e., RTCOUT). The output clock pin

should be left floating.

2.21 Dedicated LED Flasher

The LED flasher feature enables an external pin

(PD[0] / LEDFLSH) to be toggled at a programma-

ble rate and duty ratio for connection to an LED.

This module is driven from the RTCs 32.768 kHz

oscillator and works in all running modes because

no CPU intervention is needed once its rate and

duty ratio have been configured (via the LEDFLSH

register). The LED flash rate period can be pro-

grammed for 1, 2, 3, or 4 seconds. The duty ratio

can be programmed such that the mark portion can

be 1/16 to 16/16 of the full cycle.

2.22 PWM Interfaces

Two Pulse Width Modulator (PWM) duty ratio

clock outputs are provided in the CS89712. When

the device is operating from the internal PLL, the

PWM will run at a frequency of 96 kHz. These sig-

nals are intended for use as drives for external DC-

to-DC converters in the Power Supply Unit (PSU)

subsystem. External input pins that would normally

be connected to the output from comparators mon-

itoring the external DC-to-DC converter output are

also used to enable these clocks. These are the

FB[1:0] pins. The duty ratio (and hence PWMs on

time) can be programmed from 1 in 16 to 15 in 16.

The sense of the PWM drive signal (active high or

low) is determined by latching the state of this

drive signal during power on reset (i.e., a pull-up on

the drive signal will result in a active low drive out-

put, and visa versa). This allows either positive or

negative voltages to be generated by the external

DC-to-DC converter.The DC to DC converter

channels remain enabled in Snooze State. In

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