CS89712-CB 查看數據表（PDF） - Cirrus Logic

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CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

nals nRAS nCAS, and nWE are provided for

SDRAM. Two chip selects are provided for sup-

porting up to 2 rows of SDRAMs. The SDRAM

devices are put into self-refresh mode when the

SDRAM controller is put into standby. The

SDRAM clock is halted as well.

The controller supports read, write, refresh, pre-

charge and mode register write requests to the

SDRAM. Data is transferred to and from the

SDRAM as unbroken quad accesses (either quad

word or for 16 bit memory, quad halfword), which

is a convenient data packet size for the ARM cache

line fills. For the CPU to read smaller than a quad

access, the SDRAM controller will discard the ex-

tra data. For CPU writes smaller than a quad ac-

cess, the SDQM pins (SDRAM data byte mask

selects) are used to force the SDRAMs to ignore in-

valid data. For CPU access sizes larger than a quad

access, multiple quad accesses are issued to the

SDRAM.

The SDRAM controller can access a total memory

size of 2-64 Mbytes. Each individual SDRAM

should be NEC or compatible SDRAM memory in

sizes of 16-256 Mbits, arranged as shown in

Table 14 and Table 15.

Chip selects for row 1 SDRAMs should be con-

nected to nSDCS[0]. If row 2 is used, these devices

should connect to nSDCS[1].

For 32-bit memory access, four SDQM data byte

mask selects are provided to control individual byte

lanes within each row. For 16-bit memory access

only, SDQM[1:0] are used. For a 32-bit memory

access configuration with each row containing two

16-bit wide SDRAMs, the high order SDRAM

should have UDQM (upper SDQM) connected to

SDQM[3] and LDQM (lower SDQM) connected to

SDQM[2]. The low order SDRAM follows the

same convention: USDQM is connected to

SDQM[1], and LDQM is connected to SDQM[0].

Memory address line multiplexing is done internal-

ly so that the address mapping is contiguous.

Table 16 indicates how the SDRAM address pins

are connected to the CPU’s address pins. Note that

small SDRAM devices will not use all of these

pins. For example, A[12:11] may not be required.

However, the bank select pins BA[1:0], are re-

quired by all SDRAMs. Smaller devices may only

have one bank, so BA1 may not be needed.

SDRAM details

Density

(Mbits)

16

64

128

Width

(bits)

4

8

16

4

8

16

32

4

8

Arrangement of SDRAMs

(C = # Columns of SDRAM, R = # Rows of SDRAM, D = # of SDRAMs)

4 Mbytes

8 Mbytes

16 Mbytes

32 Mbytes

64 Mbytes

CRDCRDCRDCRDCR

D

818

414

212

81

8

41442

8

212224

111122

41

4

Table 14. SDRAM Configurations (SDRAM 32-Bit Memory Interface)

24

DS502PP2

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