CS89712-CB 查看數據表（PDF） - Cirrus Logic

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CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

3.18.13 Line Status Register (LineST, address offset 134h)

7

6

LinkOK

C

B

PolarityOK

5:0

010100

A

LineST reports the status of the Ethernet physical interface.

F

9

10BT

E

CRS

8

RSVD

Bit

5:0

7

8

9

C

E

Description

010100: These bits provide an internal address used by the CS89712 to identify this as register

14, the Line Status Register. When reading this register, these bits will be 010100, where the

LSB corresponds to Bit 0.

LinkOK: If set, the 10BASE-T link has not failed. When clear, the link has failed, either

because the CS89712 has just come out of reset, or because the receiver has not detected

any activity (link pulses or received packets) for at least 50 ms.

RSVD: Reserved; must be a “0” when writing to this register.

10BT: If set, the CS89712 is using the 10BASE-T interface.

PolarityOK: If set, the polarity of the 10BASE-T receive signal (at the RXD+ / RXD- inputs) is

correct. If clear, the polarity is reversed. If PolarityDis (Register 13, LineCTL, Bit C) is clear, the

polarity is automatically corrected, if needed. The PolarityOK status bit shows the true state of

the incoming polarity independent of the PolarityDis control bit. Thus, if PolarityDis is clear and

PolarityOK is clear, then the receive polarity is inverted, and corrected.

CRS: This bit tells the software the status of an incoming frame. If CRS is set, a frame is cur-

rently being received. CRS remains asserted until the end of frame (EOF). At EOF, CRS goes

inactive in about 1.3 to 2.3 bit times after the last low-to-high transition of the recovered data.

Table 78. Line Status

Reset value is: 0000 0000 0001 0100

128

DS502PP2

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