CS89712-CB 查看數據表（PDF） - Cirrus Logic

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CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

3.18.3 Receiver Event Register, (RxEvent, address offset 124h)

7

Dribblebits

C

CRCerror

6

IAHash

B

Broadcast

5:0

000100

A

Individual Adr

F

9

Hashed

E

Extradata

8

RxOK

D

Runt

Alternate meaning if bits 8 and 9 are both set (see Section 2.32.7, “Receive Ethernet Port Locations” for exception

regarding Broadcast frames).

7

6

5:0

F:A

9

8

Dribblebits

IAHash

000100

Hash Table Index (see Section 2.32.7, “Receive

Ethernet Port Locations”)

Hashed = 1

RxOK = 1

RxEvent reports the status of the current received frame.

Bit

5:0

6

7

8

9

A

B

C

D

E

Description

000100: These bits identify this as register 4, the Receiver Event Register. When reading this

register, these bits will be 000100, where the LSB corresponds to Bit 0.

IAHash: If the received frame’s Destination Address is accepted by the hash filter, then this bit

is set if, and only if IAHashA (Register 5, RxCTL, Bit 6) is set, and Hashed (Bit 9) is set. See

Section 2.32.7, “Receive Ethernet Port Locations”.

Dribblebits: If set, the received frame had from one to seven bits after the last received full

byte. An "Alignment Error" occurs when Dribblebits and CRCerror (Bit C) are both set.

RxOK: If set, the received frame had a good CRC and valid length (i.e., there is not a CRC

error, Runt error, or Extradata error). When RxOK is set, then the length of the received frame

is contained at Ethernet Port offset address 0402h. If RxOKiE (Register 3, RxCFG, Bit 8) is set,

there is an interrupt.

Hashed: If set, the received frame had a Destination Address that was accepted by the hash

filter. If Hashed and RxOK (Bit 8) are set, Bits F through A of RxEvent become the Hash Table

Index for this frame [See Section 2.32.7, “Receive Ethernet Port Locations” for an exception

regarding broadcast frames!].If Hashed and RxOK are not both set, then Bits F through A are

individual event bits as defined below.

IndividualAdr: If the received frame had a Destination Address which matched the Individual

Address found at Ethernet Port offset address 0158h, then this bit is set if, and only if, RxOK

(Bit 8) is set and IndividualA (Register 5, RxCTL, Bit A) is set.

Broadcast: If the received frame had a Broadcast Address (FFFF FFFF FFFFh) as the Desti-

nation Address, then this bit is set if, and only if, RxOK is set and BroadcastA (RxCTL register

bit B) is set.

CRCerror: If set, the received frame had a bad CRC. If CRCerroriE (Register 3, RxCFG, Bit C)

is set, there is an interrupt.

Runt: If set, the received frame was shorter than 64 bytes. If RuntiE (Register 3, RxCFG, Bit D)

is set, there is an interrupt.

Extradata: If set, the received frame was longer than 1518 bytes. All bytes beyond 1518 are

discarded. If ExtradataiE (Register 3, RxCFG, Bit E) is set, there is an interrupt.

Table 68. Receiver Event

Reset value is: 0000 0000 0000 0100

Notes: 1. All RxEvent bits are cleared upon readout. The software is responsible for processing all event bits.

2. RxStatus register (Ethernet Port offset address 0400h) is the same as the RxEvent register except

RxStatus is not cleared when RxEvent is read. See Section 2.32, “Basic Receive Operation”. The value

in the RxEvent register is undefined when RxDMAOnly bit (Bit 9, Register 3, RxCFG) is set.

118

DS502PP2

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