LTC2205-14(RevA) 查看數據表（PDF） - Linear Technology

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LTC2205-14
(Rev.:RevA)

14-Bit, 65Msps ADC

Linear Technology 

BLOCK DIAGRAM

AIN+

INPUT

AIN–

S/H

FIRST PIPELINED

ADC STAGE

DITHER

SIGNAL

GENERATOR

SENSE

VCM

RANGE

SELECT

PGA

BUFFER

VOLTAGE

REFERENCE

SECOND PIPELINED

ADC STAGE

THIRD PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

ADC CLOCKS

ADC

REFERENCE

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK

DRIVER

CONTROL

LOGIC

ENC+ ENC–

SHDN PGA RAND M0DE OE DITH

Figure 1. Functional Block Diagram

LTC2205-14

VDD

FIFTH PIPELINED

ADC STAGE

GND

CORRECTION LOGIC

AND

SHIFT REGISTER

OUTPUT

DRIVERS

OVDD

CLKOUT+

CLKOUT–

OF

D13

• D12

•

• D1

D0

OGND 220514 F01

TIMING DIAGRAM

ANALOG

INPUT

ENC–

ENC+

D0-D13, OF

CLKOUT+

CLKOUT –

tAP

N+1

N

tH

tL

N+2

N+3

tD

N–7

tC

N–6

N–5

N–4

N+4

N–3

220514 TD01

220514fa

13

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