CS44L10 查看數據表（PDF） - Cirrus Logic

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CS44L10

Digital PWM Headphone Monitor

Cirrus Logic 

CS44L10

7. CONTROL PORT INTERFACE

The control port is used to load all the internal set-

tings. The operation of the control port may be

completely asynchronous with the audio sample

rate. However, to avoid potential interference prob-

lems, the control port pins should remain static if

no operation is required.

The CS44L10 has MAP auto increment capability,

enabled by the INCR bit in the MAP register,

which is the MSB. If INCR is 0, then the MAP will

stay constant for successive writes. If INCR is set

to 1, then MAP will auto increment after each byte

is written, allowing block reads or writes of succes-

sive registers.

7.1 Two-Wire Format

SDA is a bidirectional data line. Data is clocked

into and out of the part by the clock, SCL, with a

clock to data relationship as shown in Figure 7. The

receiving device should send an acknowledge

(ACK) after each byte received. Pins AD0 and

AD1 forms the partial chip address and should be

tied to VL or GND as required. The upper 6 bits of

the 7- bit address field must be 001000.

Note: MCLK is required during all two-wire

transactions. The Two-Wire format is compatible

with the I2C protocol.

7.1.1 Writing in Two-Wire Format

To communicate with the CS44L10, initiate a

START condition of the bus. Next, send the chip

address. The eighth bit of the address byte is the

R/W bit (low for a write). The next byte is the

Memory Address Pointer, MAP, which selects the

register to be read or written. The MAP is then fol-

lowed by the data to be written. To write multiple

registers, continue providing a clock and data,

waiting for the CS44L10 to acknowledge between

each byte. To end the transaction, send a STOP

condition.

7.1.2 Reading in Two-Wire Format

To communicate with the CS44L10, initiate a

START condition of the bus. Next, send the chip

address. The eighth bit of the address byte is the

R/W bit (high for a read). The contents of the reg-

ister pointed to by the MAP will be output after the

chip address. To read multiple registers, continue

providing a clock and issue an ACK after each

byte. To end the transaction, send a STOP condi-

tion.

SDA

001000

ADDR

AD0

R/W ACK

Note 1

DATA

1-8

ACK

DATA

1-8

ACK

SCL

Start

Stop

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Figure 7. Control Port Timing, Two-Wire Format

28

DS541PP1

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