CS43L41 查看數據表（PDF） - Cirrus Logic

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CS43L41

Low Power 24-Bit, 96 kHz DAC with Volume Control

Cirrus Logic 

CS43L41

3. REGISTER QUICK REFERENCE

** “default” ==> bit status after power-up-sequence or reset.

3.1 MCLK Control (address 00h)

7

Reserved

0

6

Reserved

0

5

Reserved

0

4

Reserved

0

3

Reserved

0

2

Reserved

0

MCLKDIV (MCLK Divide-by-2 Enable)

Default = ‘0’.

0 - Disabled

1 - Enabled

3.2 Mode Control (address 01h)

7

AMUTE

1

6

DIF2

0

5

DIF1

0

4

DIF0

0

3

DEM1

0

2

DEM0

0

AMUTE (Auto-mute)

Default = ‘1’.

0 - Disabled

1 - Enabled

DIF2, DIF1 and DIF0 (Digital Interface Format)

Default = ‘0’.

0 - Format 0, I2S, up to 24-bit data, 64 x Fs Internal SCLK

1 - Format 1, I2S, up to 24-bit data, 32 x Fs Internal SCLK

2 - Format 2, Left Justified, up to 24-bit data

3 - Format 3, Right Justified, 24-bit Data

4 - Format 4, Right Justified, 20-bit Data

5 - Format 5, Right Justified, 16-bit Data

6 - Format 6, Right Justified, 18-bit Data

7 - Identical to Format 1

DEM 1, DEM 0 (De-Emphasis Mode)

Default = ‘0’.

0 - Disabled

1 - 44.1 kHz De-Emphasis

2 - 48 kHz De-Emphasis

3 - 32 kHz De-Emphasis

POR (Power on/off Quiescent Voltage ramp)

Default = ‘1’.

0 - Disabled

1 - Enabled

PDN (Power-Down)

Default =’1’.

0 - Disabled

1 - Enabled

1

MCLKDIV

0

1

POR

1

0

Reserved

0

0

PDN

1

DS473PP1

13

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