CS42L50 查看數據表（PDF） - Cirrus Logic
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CS42L50 Datasheet PDF : 48 Pages
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CS42L50
SWITCHING CHARACTERISTICS (TA = -10 to 70° C; VA = 1.7 V - 3.3 V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20 pF)
Parameters
Symbol
Min
Typ Max Units
Input Sample Rate
Single Speed Mode
Fs
Double Speed Mode
Fs
2
-
50
kHz
50
-
100
kHz
MCLK Pulse Width High
MCLK/LRCK = 1024
8
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 1024
8
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 768
MCLK Pulse Width Low
MCLK/LRCK = 768
MCLK Pulse Width High
MCLK/LRCK = 512
MCLK Pulse Width Low
MCLK/LRCK = 512
MCLK Pulse Width High MCLK / LRCK = 384 or 192
10
-
-
ns
10
-
-
ns
15
-
-
ns
15
-
-
ns
25
-
-
ns
MCLK Pulse Width Low MCLK / LRCK = 384 or 192
25
-
-
ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128
35
-
-
ns
MCLK Pulse Width Low MCLK / LRCK = 256 or 128
35
-
-
ns
Master Mode
SCLK Falling to LRCK Edge
SCLK Falling to SDOUT Valid
SCLK Duty Cycle
tslrd
-20
-
20
ns
tsdo
0
-
20
ns
40
50
60
%
Slave Mode
LRCK Duty Cycle
40
50
60
%
Rise Time of Both LRCK and SCLK
Fall Time of Both LRCK and SCLK
SCLK Period (Note 16)
Single Speed Mode
Double Speed Mode
tr
tf
tsclkw
tsclkw
-
-
(---1---2----81---)---F----s-
(---6---4--1--)--F----s--
-
10
ns
-
10
ns
-
-
ns
-
-
ns
SCLK Falling to LRCK Edge
tslrd
SCLK Falling to SDOUT Valid Single Speed Mode tdss
Double Speed Mode
tdss
-20
-
20
ns
-
-
1
ns
(512)Fs
-
-
1
ns
(256)Fs
16. There must be exactly 32, 48, 64, or 128 SCLK periods per LRCK transition.
12
DS544PP1
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