Z8038018FSC 查看數據表（PDF） - Zilog
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Z8038018FSC Datasheet PDF : 115 Pages
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ZILOG
GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUP
MICROPROCESSOR
Mnemonic
DAA
CPL[A]
CPLW[HL]
NEG[A]
NEGW[HL]
EXTS [A]
EXTSW [HL]
CCF
SCF
NOP
HALT
SLP
DI #
DI n #
EI #
EI n #
IM 0
IM 1
IM 2
IM 3
LDCTL SR,A
LDCTL SR,n
LDCTL HL,SR
Symbolic
Operation
Flags
P/
SZ x Hx VNC
@
A ← NOT A
One’s complement
HL ← NOT HL
One’s complement
A ← 0-A
Two’s complement
HL ← 0-HL
Two’s complement
L←A
H ← 00 if D7 = 0
H ← FF if D7 = 1
HLz ← 0000 if H[7] = 0
HLz ← FFFF if H[7] = 1
CY ← NOT CY
Complement carry flag
CY ← 1
No operation
CPU halted
Sleep
¤ ¤ x ¤ x P• ¤
••x1x•1•
••x1x•1•
¤ ¤ x ¤ x V1¤
¤ ¤ x ¤ x V1¤
••x•x•••
••x•x•••
• • x ¤ x • 0¤
••x0x•01
••x•x•••
••x•x•••
••x•x•••
SR(5) ← 0
IER(i) ← 0 if n(i) = 1
SR(5) ← 0 if n(0) = 1
••x•x•••
••x•x•••
SR(5) ← 1
IER(i) ← 1 if n(i) = 1
SR(5) ← 1 if n(0) = 1
••x•x•••
••x•x•••
Set INT mode 0
••x•x•••
Set INT mode 1
••x•x•••
Set INT mode 2
••x•x•••
Set INT mode 3
SR(31-24) ← A
SR(23-16) ← A
SR(15-8) ← A
SR(31-24) ← n
SR(23-16) ← n
SR(15-8) ← n
HL(15-0) ← SR(15-0)
••x•x•••
••x•x•••
••x•x•••
••x•x•••
Opcode
76 543 210
00 100 111
00 101 111
11 011 101
00 101 111
11 101 101
01 000 100
11 101 101
01 010 100
11 101 101
01 100 101
11 101 101
01 110 101
00 111 111
00 110 111
00 000 000
01 110 110
11 101 101
01 110 110
11 110 011
11 011 101
11 110 011
← n →
11 111 011
11 011 101
11 111 011
← n →
11 101 101
01 000 110
11 101 100
01 010 101
11 101 101
01 011 110
11 101 101
01 001 110
11 011 101
11 001 000
11 011 101
11 001 010
← n →
11 101 101
11 000 000
# of Execute
HEX Bytes Time Notes
27
13
2F
12
DD 2 2
2F
ED 1 2
44
ED 1 2
54
ED 2 3
L9
65
ED
3
75
3F
12
37
12
00
12
76
12
ED 2 2
76
F3
12
DD 3 2
F3
FB
12
DD 3 2
FB
ED 2 4
46
ED 2 4
56
ED 2 4
5E
ED 2 4
4E
DD 2 4
C8
DD 3 4
CA
ED 2 2
L1
C0
PS010001-0301
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