Z8038018FSC 查看數據表（PDF） - Zilog

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Z8038018FSC

MICROPROCESSOR

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EXTERNAL INTERFACE (Continued)

Interrupt Acknowledge Transactions

An interrupt acknowledge transaction is generated by the

Z380 MPU in response to an unmasked external interrupt

request. Figure 10A shows an interrupt acknowledge

transaction in response to /INT0 and Figure 10B shows an

interrupt acknowledge transaction in response to either

one of /INT-3. Note that because all I/O bus transactions

MICROPROCESSOR

start on a rising edge of IOCLK, there may be up to n

BUSCLK cycles of latency between the execution unit

request for the transaction and the transaction actually

starting (where n is the programmed clock divisor for

IOCLK).

IOCLK

ADDRESS

DATA

/WAIT

/M1

/IORQ

/IORD

/IOWR

/INTAK

Figure 10A. Interrupt Acknowledge Cycle, /INT0

PS010001-0301

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