CS8401A-CS 查看數據表（PDF） - Cirrus Logic

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CS8401A-CS

Digital Audio Interface Transmitter

Cirrus Logic 

CS8402A

C2 is tied high, channel status bit 2 will be trans-

mitted as a zero. Also, FC0 and FC1 are encoded

versions of channel status bits 24 and 25, which

define the sample frequency. When FC0 and FC1

are both high, the part is placed in a CD sub-

mode which activates the CD subcode port. This

submode is described in detail in the next sec-

tion. Table 5 describes the encoding of C24 and

C25 through the FC1 and FC0 pins. According

to AES/EBU standards, C2 is copy prohibit/per-

mit, C3 specifies pre-emphasis, C8 and C9

define the category code, and C15 identifies the

generation status of the transmitted material (i.e..

first generation, second generation).

Consumer - CD Submode

The consumer CD submode is invoked by plac-

ing the part in consumer mode (PRO = high) and

setting both FC1 and FC0 high. This mode rede-

fines some of the pins for a CD subcode port as

shown in Figure 21. The CD subcode port pins,

SBF and SBC, replace the C and CBL pins respec-

tively. The user data input, U, becomes the CD

subcode input. Figure 22 describes the timing for

the CD subcode port. When SBF is low, SBC be-

comes active, clocking in the subcode bits. SBF

goes high for one SCK period, one half SCK pe-

riod after the active edge of FSYNC for all formats

(except format 4, which will be one and a half

SCK periods after the active edge of FSYNC). SBF

high for more than 16 SBC periods indicates the

start of a subcode block. The first, third, and fourth

Q bits after the start of a subcode block become

channel status bits 5, 2, and 3 respectively. Chan-

nel status bits are set by the dedicated pins; the

category code is forced to CD.

EM1

EM0

C2

C3

C4

0

0

1

1

1

0

1

1

1

0

1

0

1

0

0

1

1

0

0

0

FC1 FC0

0

0

0

1

1

0

1

1

C24 C25

Comments

0

0 44.1 kHz

0

1 48.0 kHz

1

1 32.0 kHz

0

0 44.1 kHz, CD Mode

SDATA

SCK

FSYNC

Table 4. Emphasis Encoding

M2 M1 M0

23 22 21

8

Serial

6

Port

7

Logic

C 10

U 11

V9

Registers

Table 5. Sample Frequency Encoding

Audio

Aux

C Bits

U Bits

Validity

Preamble

Parity

Biphase

Mux

Mark

Encoder

20

Line

Driver

17

TXP

TXN

Timing

16

RST

+5V

2 3 24 4 1 13 14 12

15 5

PRO FC0 FC1 C2 C3 C8 C9 C15

CBL MCK

Figure 20. CS8402A Block Diagram - Consumer Mode

DS60F1

23

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