QL6250-7PS484M 查看數據表（PDF） - QuickLogic Corporation

零件编号

产品描述 (功能)

生产厂家

QL6250-7PS484M

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Eclipse Family Data Sheet Rev. F

Clock Networks

Global Clocks

There are eight global clock networks in the Eclipse device family. Global clocks can drive logic cell, I/O, and

RAM blocks in the device. Five global clocks have access to a Quad Net (local clock network) connection with

a programmable connection to the register inputs. Global clock pins are 2.5 V, LVCMOS2, compliant.

Figure 9: Global Clock Methodology

Quad Net

Global Clock Net

CLK Pin

12

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