Z86C4016FEC 查看數據表（PDF） - Zilog
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Z86C4016FEC Datasheet PDF : 17 Pages
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ZILOG
AC ELECTRICAL CHARACTERISTICS
Additional Timing Table (Divide-By-One Mode)
Z86C30/C31/C32/C40
CP96DZ82900
TA = 0°C to +70°C TA = 40°C to +105°C
No Symbol Parameter
V
CC
Note [6]
4 MHz
Min Max
4 MHz
Min Max
Units
1 TpC
Input Clock Period
3.0V
250 DC
250 DC
ns
5.5V
250 DC
250 DC
ns
2 TrC,TfC Clock Input Rise & Fall Times 3.0V
25
25
ns
5.5V
25
25
ns
3 TwC
Input Clock Width
3.0V
100
100
ns
5.5V
100
100
ns
4 TwTinL Timer Input Low Width
3.0V
100
100
ns
5.5V
70
70
ns
5 TwTinH Timer Input High Width
3.0V
5TpC
5TpC
5.5V
5TpC
5TpC
6 TpTin
Timer Input Period
3.0V
8TpC
8TpC
5.5V
8TpC
8TpC
7 TrTin,
Timer Input Rise & Fall Timer 3.0V
100
100
ns
TfTin
5.5V
100
100
ns
8A TwIL
Int. Request Low Time
3.0V
100
100
ns
5.5V
70
70
ns
8B TwIL
Int. Request Low Time
3.0V
5TpC
5TpC
5.5V
5TpC
5TpC
9 TwIH
Int. Request Input High Time 3.0V
5TpC
5TpC
5.5V
5TpC
5TpC
10 Twsm
STOP Mode Recovery Width Spec 3.0V
12
12
ns
5.5V
12
12
ns
11 Tost
Oscillator Start-up Time
3.0V
5TpC
5TpC
5.5V
5TpC
5TpC
Notes:
[1] Timing Reference uses 0.7 V for a logic 1 and 0.2 V for a logic 0.
CC
CC
[2] Interrupt request via Port 3 (P31-P33).
[3] Interrupt request via Port 3 (P30).
[4] SMR-D5 = 1, POR STOP Mode Delay is on.
[5] Reg. WDTMR.
[6]
The
V
CC
voltage
specification
of
3.0V
guarantees
3.3V
±
0.3V,
and
the
V
DD
voltage
specification
of
5.5V
guarantees
5.0V ±
0.5V.
[7] SMR D1 = 0.
[8] Maximum frequency for internal system clock is 4 MHz when
using XTAL divide-by-one mode.
[9] For RC and LC oscillator, and for oscillator driven by clock driver.
Notes
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,2,7,8]
[1,2,7,8]
[1,3,7,8]
[1,3,7,8]
[1,2,7,8]
[1,2,7,8]
[4,8]
[4,8]
[4,8,9]
[4,8,9]
CP96DZ82900
15
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