ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 114. Channel Manager Output Block Diagram with PWM generator delivering 3 PWM signals
PWM generator signals
W
V
U
Dead
Time
Dead
Time
Dead
Time
8 MDTG Register
PCN bit = 1
Channel [5:4] Channel [3:2] Channel [1:0]
MREF Register
2
HFE[1:0] bits
HFRQ[2:0] bits
5
High frequency chopper
MPOL Register
x6
OP[5:0] bits
OCV bit 1
MRCA Register 6
CLIM bit
1
CLI bit 1
MOE bit
1
x6
Note: The output of the current limitation comparator can be used when 3 PWM signals are enabled if the
VOC1 bit =0 in the MCRA register.
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