ST7FMC2N6B6(2004) 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

ST7FMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

INTERRUPTS (Cont’d)

6.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT

low power mode. On the contrary, only external

and other specified interrupts allow the processor

to exit from the HALT modes (see column “Exit

from HALT” in “Interrupt Mapping” table). When

several pending interrupts are present while exit-

ing HALT mode, the first one serviced can only be

an interrupt with exit from HALT mode capability

and it is selected through the same decision proc-

ess shown in Figure 19.

Note: If an interrupt, that is not able to Exit from

HALT mode, is pending with the highest priority

when exiting HALT mode, this interrupt is serviced

after the first one serviced.

Figure 20. Concurrent Interrupt Management

6.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 20 and Figure 21 show two

different interrupt management modes. The first is

called concurrent mode and does not allow an in-

terrupt to be interrupted, unlike the nested mode in

Figure 21. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN,

IT4, IT3, IT2, IT1, IT0, MCES. The software priority

is given for each interrupt.

Warning: A stack overflow may occur without no-

tifying the software of the failure.

SOFTWARE

PRIORITY

I1

I0

LEVEL

MCES

IT0

IT1

IT1

IT2

IT3

RIM

IT4

MAIN

11 / 10

MAIN

10

3

11

3

11

3

11

3

11

3

11

3

11

3/0

Figure 21. Nested Interrupt Management

IT1

IT2

RIM

MAIN

11 / 10

MCES

IT0

IT4

IT4

IT1

IT3

SOFTWARE

PRIORITY

I1

I0

LEVEL

IT2

MAIN

10

3

11

3

11

2

00

1

01

3

11

3

11

3/0

37/294

1

Share Link: