ST7PMC2N6B6(2004) 查看數據表（PDF） - STMicroelectronics

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ST7PMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Effect on PWM generator: the PWM generator

12-bit counter is reset as soon as CKE = 0; this en-

sures that the PWM signals start properly in all

cases. When these bits are set, all registers with

preload on Update event are transferred to active

registers.

Bit 5 = SR: Sensor ON/OFF.

0: Sensorless mode

1: Position Sensor mode

Table 57. Sensor Mode Selection

SR

bit

Mode

OS[2:0]

bits

0

Sensors

not used

OS[2:0]

bits

enabled

1

Sensors OS1

used disabled

Behaviour of the output

PWM

“Between Cn&D” behaviour,

“between D&Z” behaviour

and “between Z&Cn+1” be-

haviour

“Between Cn&Z” behaviour

and “between Z&Cn+1” be-

haviour

See also Table 62 and Table 63

Bit 4 = DAC: Direct Access to phase state register.

0: No Direct Access (reset value). In this mode the

preload value of the MPHST and MCRB regis-

ters is taken into account at the C event.

1: Direct Access enabled. In this mode, write a val-

ue in the MPHST register to access the outputs

directly.

Note: In Direct Access Mode (DAC bit is set in

MCRA register), a C event is generated as soon

as there is a write access to the OO[5:0] bits in

MPHST register. In this case, the PWM low/high

selection is done by the OS0 bit in the MCRB

register.

Table 58. DAC Bit Meaning

MOE

bit

0

1

1

DAC

bit

x

0

1

Effect on Output

Reset state depending on the option

bit

Standard

running mode.

MPHST register value (depending on

MPOL, MPAR register values and

PWM setting) see Table 75

Bit 3 = V0C1: Voltage/Current Mode

0: Voltage Mode

1: Current Mode

Bit 2 = SWA: Switched/Autoswitched Mode

0: Switched Mode

1: Autoswitched Mode

Table 59. Switched and Autoswitched Modes

SWA

bit

0

1

Commutation Type

Switched mode

Autoswitched mode

MCOMP Register

access

Read/Write

Read/Write

Bit 1 = PZ: Protection from parasitic Zero-crossing

event detection

0: Protection disabled

1: Protection enabled

Note: If the PZ bit is set, the Z event filter

(ZEF[3:0] in the MZFR register is ignored.

Bit 0 = DCB: Data Capture bit

0: Use MZPRV (ZN-1) for multiplication

1: Use MZREG (ZN) for multiplication

Table 60. Multiplier Result

DCB bit

0

1

Commutation Delay

MCOMP = MWGHT x MZPRV / 256

MCOMP = MWGHT x MZREG / 256

207/294

1

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