ST7PMC2N6B6(2004) 查看數據表（PDF） - STMicroelectronics

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ST7PMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

Address

Block

Register

Label

Register Name

Reset

Status

Remarks

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

PWM ART

PWMDCR3

PWMDCR2

PWMDCR1

PWMDCR0

PWMCR

ARTCSR

ARTCAR

ARTARR

ARTICCSR

ARTICR1

ARTICR2

PWM AR Timer Duty Cycle Register 3

PWM AR Timer Duty Cycle Register 2

PWM AR Timer Duty Cycle Register 1

PWM AR Timer Duty Cycle Register 0

PWM AR Timer Control Register

Auto-Reload Timer Control/Status Register

Auto-Reload Timer Counter Access Register

Auto-Reload Timer Auto-Reload Register

AR Timer Input Capture Control/Status Reg.

AR Timer Input Capture Register 1

AR Timer Input Capture Register 2

00h

R/W

00h

R/W

00h

R/W

00h

R/W

00h

R/W

00h

R/W

00h

R/W

00h

R/W

00h

R/W

00h

Read Only

00h

Read Only

007Fh

OPAMP

OACSR

OPAMP Control/Status Register

00h

R/W

Legend: x=undefined, R/W=read/write

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-

tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

19/294

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