SST32HF3242C-70-4C-LS 查看數據表（PDF） - Silicon Storage Technology

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SST32HF3242C-70-4C-LS

Multi-Purpose Flash Plus + SRAM ComboMemory

Silicon Storage Technology 

Preliminary Specifications

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282

SST32HF1622C / SST32HF1642C / SST32HF3242C

ADDRESSES AMSF-0

BEF#

OE#

WE#

DQ6 and DQ2

TOEH

TCE

TOE

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF16x2x and A20 for SST32HF32x2x

FIGURE 10: FLASH TOGGLE BIT TIMING DIAGRAM

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

1253 F10.0

ADDRESS AMS-0

SIX-BYTE CODE FOR CHIP-ERASE

5555 2AAA

5555

5555

2AAA

5555

TSCE

BEF#

OE#

WE#

TWP

DQ15-0

XXAA XX55

XX80

XXAA

XX55

XX10

SW0

SW1

SW2

SW3

SW4

SW5

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF16x2x and A20 for SST32HF32x2x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

This device also supports BEF# controlled Chip-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 14)

X can be VIL or VIH, but no other value.

FIGURE 11: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM

1253 F11.0

©2005 Silicon Storage Technology, Inc.

20

S71253-03-000

5/05

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