SI5328C-C-GM 查看數據表（PDF） - Silicon Laboratories

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SI5328C-C-GM

ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5328

Pin # Pin Name I/O Signal Level

Description

4

C2B

O LVCMOS CKIN2 Invalid Indicator.

This pin functions as a LOS (and optionally FOS) alarm indicator for

CKIN2 if CK2_BAD_PIN = 1.

0 = CKIN2 present

1 = LOS (FOS) on CKIN2

The active polarity can be changed by CK_BAD_POL. If

CK2_BAD_PIN = 0, the pin tristates.

5, 10, 32

VDD

VDD

Supply Supply.

The device operates from a 2.5 or 3.3 V supply. Bypass capacitors

should be associated with the following VDD pins:

5

0.1 µF

10 0.1 µF

32 0.1 µF

A 1.0 µF should also be placed as close to the device as is practical.

7

XB

I

Analog Reference Clock.

6

XA

A TCXO or OCXO should be connected to these pins. Refer to the

Si53xx Family Reference Manual for interfacing to the external ref-

erence. External reference must be from a high-quality clock source

(TCXO, OCXO). Frequency of crystal or external clock is set by

RATE[1:0] pins.

8, 31

GND

GND

Supply

Ground.

Must be connected to system ground. Minimize the ground path

impedance for optimal performance of this device. Grounding these

pins does not eliminate the requirement to ground the GND PAD on

the bottom of the package.

11

RATE0 I

3-Level Reference Clock Rate.

15

RATE1

Three level inputs that select the type and rate of external crystal or

reference clock to be applied to the XA/XB port. Refer to the Si53xx

Family Reference Manual for settings. These pins have both a weak

pull-up and a weak pull-down; they default to M.

L setting corresponds to ground.

M setting corresponds to VDD/2.

H setting corresponds to VDD.

Some designs may require an external resistor voltage divider when

driven by an active device that will tristate.

16

CKIN1+ I

17

CKIN1–

Multi

Clock Input 1.

Differential input clock. This input can also be driven with a single-

ended signal.

12

CKIN2+ I

13

CKIN2–

Multi

Clock Input 2.

Differential input clock. This input can also be driven with a single-

ended signal.

Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.

Rev. 1.0

59

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