SI5328C-C-GMR 查看數據表（PDF） - Silicon Laboratories

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SI5328C-C-GMR

ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5328

Register 136.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name RST_REG ICAL

Reserved

Type

R/W

R/W

R

Reset value = 0000 0000

Bit

Name

Function

7

RST_REG Internal Reset (Same as Pin Reset).

Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.

0: Normal operation.

1: Reset of all internal logic. Outputs disabled or tristated during reset.

6

ICAL

Start an Internal Calibration Sequence.

For proper operation, the device must go through an internal calibration sequence. ICAL

is a self-clearing bit. Writing a “1” to this location initiates an ICAL. The calibration is com-

plete once the LOL alarm goes low.

0: Normal operation.

1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-calibra-

tion, LOL will go low.

Notes:

1. A valid stable clock (within 100 ppm) must be present to begin ICAL.

2. If the input changes by more than 500 ppm, the part may do an autonomous ICAL.

3. See Table 10, “Register Locations Requiring ICAL,” on page 62 for register changes that

require an ICAL.

5:0 Reserved Reserved.

Register 137.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

FASTLOCK

Type

R

R

R

R

R

R

R

R/W

Reset value = 0000 0000

Bit

Name

Function

7:1

Reserved Do not modify.

0

FASTLOCK This bit must be set to 1 to enable FASTLOCK. This improves initial lock time by

dynamically changing the loop bandwidth.

54

Rev. 1.0

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