CS8415A-IS 查看數據表（PDF） - Cirrus Logic

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CS8415A-IS

96 kHz Digital Audio Interface Receiver

Cirrus Logic 

CS8415A

15. APPENDIX B: CHANNEL STATUS AND

USER DATA BUFFER MANAGEMENT

15.1 AES3 Channel Status (C) Bit

Management

The CS8415A contains sufficient RAM to store a

full block of C data for both A and B channels (192

x 2 = 384 bits), and also 384 bits of U information.

The user may read from these buffer RAMs

through the control port.

The buffering scheme involves 2 block-sized buff-

ers, named D and E, as shown in Figure 15. The

MSB of each byte represents the first bit in the se-

rial C data stream. For example, the MSB of byte 0

(which is at control port address 20h) is the con-

sumer/professional bit for channel status block A.

The first buffer (D) accepts incoming C data from

the AES receiver. The 2nd buffer (E) accepts entire

blocks of data from the D buffer. The E buffer is

also accessible from the control port, allowing

reading of the C data.

15.2 Accessing the E buffer

The user can monitor the incoming data by reading

the E buffer, which is mapped into the register

space of the CS8415A, through the control port.

The user can configure the interrupt enable regis-

ter to cause interrupts to occur whenever D to E

buffer transfers occur. This allows determination of

the allowable time periods to interact with the E

buffer.

Also provided is a D to E inhibit bit. This may be

used whenever “long” control port interactions are

occurring.

A flowchart for reading the E buffer is shown in

Figure 16. Since a D to E interrupt just occurred af-

ter reading, there is a substantial time interval until

the next D to E transfer (approximately 24 frames

worth of time). This is usually plenty of time to ac-

cess the E data without having to inhibit the next

transfer.

15.2.1 Reserving the first 5 bytes in the E

buffer

D to E buffer transfers periodically overwrite the

data stored in the E buffer. The CS8415A has the

capability of reserving the first 5 bytes of the E buff-

er for user writes only. When this capability is in

use, internal D to E buffer transfers will NOT affect

the first 5 bytes of the E buffer. Therefore, the user

can set values in these first 5 E bytes once, and the

settings will persist until the next user change. This

mode is enabled using the Channel Status Data

Buffer Control register.

From

AES3

Receiver

D

Received

Data

Buffer

A

B

8-bits 8-bits

E

24

words

Control Port

Figure 15. Channel Status Data Buffer Structure

D to E interrupt occurs

Optionally set D to E inhibit

Read E data

If set, clear D to E inhibit

Return

Figure 16. Flowchart for Reading the E Buffer

38

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