CS8415A-IS 查看數據表（PDF） - Cirrus Logic

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CS8415A-IS

96 kHz Digital Audio Interface Receiver

Cirrus Logic 

CS8415A

8. CONTROL PORT REGISTER BIT DEFINITIONS

8.1 Control 1(01h)

7

SWCLK

6

5

4

0

MUTESAO

0

3

2

1

0

0

INT1

INT0

0

SWCLK - Controls output of OMCK on RMCK when PLL loses lock

Default = ‘0’

0 - RMCK default function

1 - OMCK output on RMCK pin

MUTESAO - Mute control for the serial audio output port

Default = ‘0’

0 - Disabled

1 - Enabled

INT1:0 - Interrupt output pin (INT) control

Default = ‘00’

00 - Active high; high output indicates interrupt condition has occurred

01 - Active low, low output indicates an interrupt condition has occurred

10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.

11 - Reserved

8.2 Control 2 (02h)

7

6

5

4

3

2

1

0

0

HOLD1

HOLD0

RMCKF

MMR

MUX2

MUX1

MUX0

HOLD1:0 - Determine how received audio sample is affected when a receiver error occurs

Default = ‘00’

00 - Hold the last valid audio sample

01 - Replace the current audio sample with 00 (mute)

10 - Do not change the received audio sample

11 - Reserved

RMCKF - Select recovered master clock output pin frequency.

Default = ‘0’

0 - RMCK is equal to 256 * Fs

1 - RMCK is equal to 128 * Fs

MMR - Select AES3 receiver mono or stereo operation

Default = ‘0’

0 - Normal stereo operation

1 - A and B subframes treated as consecutive samples of one channel of data.

Data is duplicated to both left and right parallel outputs of the AES receiver block.

The sample rate (Fs) is doubled compared to MMR=0

20

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