SC4524BSETRT 查看數據表（PDF） - Semtech Corporation

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SC4524BSETRT

18V 2A Step-Down Switching Regulator

Semtech Corporation 

SC4524B

Applications Information (Cont.)

CONTROLLER AND SCHOTTKY DIODE

Io

CA

Rs

Including the voltage divider (R4 and R6), the control to

feedback transfer function is found and plotted in Figure

REF

+

EA

FB

-

Vc

Vramp

PWM

MODULATOR

COMP

C5

C8

R7

SW

L1

Co

Resr

Vo

R4

R6

8 as the converter gain.

Since the converter gain has only one dominant pole at

low frequency, a simple Type-2 compensation network

is sufficient for voltage loop compensation. As shown in

Figure 8, the voltage compensator has a low frequency

integrator pole, a zero at FZ1, and a high frequency pole

at FP1. The integrator is used to boost the gain at low

frequency. The zero is introduced to compensate the

excessive phase lag at the loop gain crossover due to the

Figure 7. Block diagram of control loops

integrator pole (-90deg) and the dominant pole (-90deg).

TbhueckbcloAAocnCCkv==deir−−ateg22rr00awm⋅⋅illtoohinggtFhGGiegCCuSAArRRCe4SS75⋅⋅2s22h4ππoBFFw.CCTsCChteOOhie⋅⋅nVcVnVVoFFOeOBBnrtlrooolplo(ocpusrroefnat

The high frequency pole nulls the ESR zero and attenuates

high frequency noise.

O

⋅

VFB

VO



laloonoodppa) (vccAAuooCCrlntr==aseigns−−etts22al00omoof⋅⋅pplloaol)iggficceuo2r2rn(88rCsei⋅⋅Ans66tt)s..wsoei⋅⋅tfnhas00ignn−−a3g3einr⋅⋅rr2(o2eGsrππCisaA⋅⋅t=m88o200rp8⋅⋅l()iR.fiTs00e=hr336e(.⋅⋅1Eo22Amu22)tW,⋅e⋅ ar)

PWM modulator, and a LC filter.

00

−−66

⋅⋅ 33....003360 == 55..99ddBB

30

Fz1

Fp1

=⋅⋅⋅ll52oo0.9ggπ.4⋅5G28n80CFAStcFicg⋅n⋅Raoooii6nvdsSmnr.k0ecute⋅npar3cfo2⋅otetbRRCC⋅CCalchrπn2y0n77(o5858FestV2:chnCa−======Cce3C⋅tve)uo00e2222OL⋅trlr0r.o.oπ1πr2ππ22t(,⋅e−oeCπ⋅⋅⋅⋅o88on6VV0pr0665uuF⋅t,O⋅⋅60⋅60B8tRwtc22l553p0o00p0..o09⋅97⋅00i,.u.outm03⋅⋅a⋅−−htp0t033np(00c330idVse==sa3w3⋅⋅3OnpCi2222)n⋅⋅is⋅a8t522222t2a)t2ccr.e.t..2.2ahi2933itron..iandkkn⋅⋅⋅nsnaBgf⋅⋅cle0i0l0esyrf−0033r6ftcCeuo33l==Oqo⋅n=d=3us0a0ceene.t...0344idsndo22i,55cgnpptlnnyn=oFhFiFFanetFdh5SFriWeeni.g,9mgvudooarRBueiln,ttap7tinghuigeest

0

-30

-60

1K

Fp

COMPENSATOR GAIN

CONVERTER GAIN Fc

LOOP GAIN

Fz Fsw/2

10K

100K

1M

10M

FREQUENCY (Hz)

20

⋅6=⋅0−023p3=F⋅ T22h22is..3trk⋅aVVVV nococ0s==f3er((=f u0++n.4ssc5t//inGGoωωFnP PppWW))hMM((a((s++a++ss fss//inRRωωiEEtnnSSeQQRRDCC ++COOss))g22a//inωωnn22 ))

(8)

Figure 8. Bode plots for voltage loop design

Therefore, the procedure of the voltage loop design for



200/ ω⋅ n2 0) 3

⋅ 22.GG⋅PPWW0MM3≈≈=GGCCA2ARRp⋅⋅RRFSS

,,

ωωpp

≈≈



RRCCOO

,,

ωωZZ == RR EESSRRCCt(1hOO)e,,PSloCt4t5h2e4cBocnavnerbteersguaminm, ia.eri.zceodnatrso: l to feedback transfer

ARR/⋅CGRωOPSpW,),M((+aan+sdsEo/RSmωREnRωRCCCCSiωnQzR775Z858peaC+rn====≈===Oots)RR2222Fl2ggo00CEZππππ/SmwmaAOAF2FF2FRωCC00t-CPZPZ,fn2rO)eRRRR,q7777uencyωpZo=leRFEPSaRtCO ,

and double poles at half the switching frequency.

R4

=

R

6







VO

.0 V

−  



function.

(2) Select the open loop crossover frequency, FC, between

10% and 20% of the switching frequency. At FC, find the

required compensator gain, AC. In typical applications with

ceramic output capacitors, the ESR zero is neglected and

the required compensator gain at FC can be estimated by

A C = − 20 ⋅ log  GCAR S ⋅ 2πF CC O ⋅ VVFOB 

(9)

AC

=

−

2

0

⋅

log



2

8

⋅

6

.





⋅



0

−3

⋅

2

π

⋅

8

0

⋅





03

13

⋅ 22 ⋅0 −6

⋅ .0

3.

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