PSD935G3V-C-15UI 查看數據表（PDF） - STMicroelectronics
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PSD935G3V-C-15UI Datasheet PDF : 91 Pages
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PSD935G2
PSD9XX Family
Microcontroller Interface – PSD935G2 AC/DC Parameters
(5V ± 10% Versions)
Read Timing (5 V ± 10% Versions)
Symbol
t LVLX
t AVLX
t LXAX
t AVQV
t SLQV
t RLQV
t RHQX
t RLRH
t RHQZ
t EHEL
t THEH
t ELTL
t AVPV
Parameter
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Data Valid
CS Valid to Data Valid
RD to Data Valid
RD or PSEN to Data Valid,
80C51 Mode
RD Data Hold Time
RD Pulse Width
RD to Data High-Z
E Pulse Width
R/W Setup Time to Enable
R/W Hold Time After Enable
Address Input Valid to Address
Output Delay
Conditions
(Note 3)
(Note 3)
(Note 3)
(Note 5)
(Note 2)
(Note 1)
(Note 1)
(Note 1)
(Note 4)
-70
Min Max
15
4
7
70
75
24
-90
Min Max
20
6
8
90
100
32
Turbo
Off Unit
ns
ns
ns
Add 12 ns
ns
ns
31
38
ns
0
0
ns
27
32
ns
20
25
ns
27
32
ns
6
10
ns
0
0
ns
20
25
ns
NOTES: 1.
2.
3.
4.
5.
RD timing has the same timing as DS and PSEN signals.
RD and PSEN have the same timing.
Any input used to select an internal PSD935G2 function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
RD timing has the same timing as DS signals.
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