PSD935G3V-C-15UI 查看數據表（PDF） - STMicroelectronics

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PSD935G3V-C-15UI

Configurable Memory System on a Chip for 8-Bit Microcontrollers

STMicroelectronics 

PSD935G2

The

PSD935G2

Functional

Blocks

(cont.)

Figure 24. APD Logic Block

PSD9XX Family

APD EN

PMMR0 BIT 1=1

TRANSITION

DETECTION

ALE

RESET

CSI

CLKIN

EDGE

DETECT

CLR PD

APD

COUNTER

PD

DISABLE MAIN AND

SECONDARY FLASH/SRAM

DISABLE BUS

INTERFACE

SECONDARY

FLASH SELECT

PLD

MAIN FLASH SELECT

SRAM SELECT

POWER DOWN

(PDN) SELECT

Figure 25. Enable Power Down Flow Chart

RESET

Enable APD

Set PMMR0 Bit 1 = 1

OPTIONAL

Disable desired inputs to PLD

by setting PMMR0 bit 4

and PMMR2 bits 0.

No

ALE/AS idle

for 15 CLKIN

clocks?

Yes

PSD in Power

Down Mode

57

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