PSD812G3V-C-20UI 查看數據表（PDF） - STMicroelectronics
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PSD812G3V-C-20UI Datasheet PDF : 110 Pages
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PSD8XX Family
PSD835G2
Microcontroller Interface – PSD835G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Port F Peripheral Data Mode Read Timing (3.0 V to 3.6 V Versions)
Symbol
Parameter
Conditions
-90
-12
Turbo
Min Max Min Max Off Unit
t AVQV (PF)
t SLQV (PF)
t RLQV (PF)
t DVQV (PF)
t QXRH (PF)
t RLRH (PF)
t RHQZ (PF)
Address Valid to Data Valid
CSI Valid to Data Valid
RD to Data Valid
RD to Data Valid, 8031 Mode
Data In to Data Out Valid
RD Data Hold Time
RD Pulse Width
RD to Data High-Z
(Note 3)
(Notes 1 and 4)
(Note 1)
(Note 1)
50
50 Add 20 ns
35
40 Add 20 ns
35
40
ns
45
45
ns
34
38
ns
0
0
ns
35
36
ns
38
40
ns
Port F Peripheral Data Mode Write Timing (3.0 V to 3.6 V Versions)
Symbol
Parameter
Conditions
t WLQV (PF)
t DVQV (PF)
t WHQZ (PF)
WR to Data Propagation Delay
Data to Port F Data Propagation
Delay
WR Invalid to Port F Tri-state
(Note 2)
(Note 5)
(Note 2)
NOTES: 1.
2.
3.
4.
5.
RD timing has the same timing as DS and PSEN signals.
WR timing has the same timing as E and DS signals.
Any input used to select Port F Data Peripheral Mode.
Data is already stable on Port F.
Data stable on ADIO pins to data on Port F.
-90
-12
Min Max Min Max Unit
40
43 ns
35
38 ns
33
33 ns
92
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