PSD812G3V-C-15M 查看數據表（PDF） - STMicroelectronics
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PSD812G3V-C-15M Datasheet PDF : 110 Pages
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PSD8XX Family
PSD835G2
PSD835G2 AC/DC Parameters – GPLD Timing Parameters
(3.0 V to 3.6 V Versions)
GPLD Micro⇔Cell Asynchronous Clock Mode Timing (3.0 V to 3.6 V Versions)
Symbol
Parameter
Conditions
-90
-12
PT TURBO Slew
Min Max Min Max Aloc OFF Rate Unit
fMAXA
t SA
t HA
t CHA
t CLA
t COA
t ARD
t MINA
Maximum Frequency
External Feedback
Maximum Frequency
Internal Feedback ( fCNTA)
Maximum Frequency
Pipelined Data
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output Delay
GPLD Array Delay
Minimum Clock Period
1/(tSA+ t CO A)
1/(tSA+ t CO A–10)
1/(tCH A+ t CLA)
Any Micro⇔Cell
1/ fCNTA
23.8
31.25
38.4
8
10
10
12
15
18
12
15
34
23
32
38
20.8
MHz
26.3
MHz
30.3
MHz
Add 4 Add 20
ns
ns
Add 20
ns
Add 20
ns
38
Add 20 Sub 6 ns
27 Add 4
ns
ns
Input Micro⇔Cell Timing (3.0 V to 3.6 V Versions)
Symbol
Parameter
-90
-12
PT
Conditions Min Max Min Max Aloc
TURBO
OFF Unit
tIS
Input Setup Time
tIH
Input Hold Time
tINH
NIB Input High Time
t IN L
NIB Input Low Time
tINO
NIB Input to Combinatorial
Delay
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
0
0
20
23
13
13
12
13
ns
Add 20 ns
ns
ns
46
62 Add 4 Add 20 ns
NOTE: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX.
88
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