PSD803G3V-C-20UI 查看數據表（PDF） - STMicroelectronics
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PSD803G3V-C-20UI Datasheet PDF : 110 Pages
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PSD8XX Family
The
PSD835G2
Functional
Blocks
(cont.)
PSD835G2
9.1.5 Memory ID Registers
The 8-bit read only memory status registers are included in the CSIOP space. The user
can determine the memory configuration of the PSD device by reading the Memory ID0
and Memory ID1 registers. The content of the registers are defined as follow:
Memory_ID0 Register
Bit 7
Bit 6
S_size 3 S_size 2
Bit 5
S_size 1
Bit 4
S_size 0
Bit 3
F_size 3
Bit 2
F_size 2
Bit 1
Bit 0
F_size 1 F_size 0
Bit Definition
F_size3
0
0
0
0
0
0
0
F_size2
0
0
0
0
1
1
1
F_size1
0
0
1
1
0
0
1
F_size0
0
1
0
1
0
1
0
Main Flash Size
(Bit)
none
256K
512K
1M
2M
4M
8M
S_size3
0
0
0
0
S_size2
0
0
0
0
S_size1
0
0
1
1
S_size0
0
1
0
1
SRAM Size
(Bit)
none
16K
32K
64K
Memory_ID1 Register
Bit 7
Bit 6
*
*
Bit 5
B_type 1
*Not used bit should be set to zero.
Bit Definition
B_size3
0
0
0
0
B_size2
0
0
0
0
Bit 4
B_type 0
Bit 3
B_size 3
B_size1
0
0
1
1
Bit 2
B_size 2
B_size0
0
1
0
1
Bit 1
Bit 0
B_size 1 B_size 0
Boot Block Size
(Bit)
none
128K
256K
512K
B_type1
0
0
B_type0
0
1
Boot Block Type
Flash
EEPROM
32
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