PSD4235G2-C-70UI 查看數據表（PDF） - STMicroelectronics
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PSD4235G2-C-70UI
STMicroelectronics
PSD4235G2-C-70UI Datasheet PDF : 91 Pages
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PSD935G2
PSD9XX Family
Microcontroller Interface – PSD935G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Read Timing (3.0 V to 3.6 V Versions)
Symbol
t LVLX
t AVLX
t LXAX
t AVQV
t SLQV
t RLQV
t RHQX
t RLRH
t RHQZ
t EHEL
t THEH
t ELTL
t AVPV
Parameter
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Data Valid
CS Valid to Data Valid
RD to Data Valid
RD or PSEN to Data Valid,
80C51 Mode
RD Data Hold Time
RD Pulse Width
RD to Data High-Z
E Pulse Width
R/W Setup Time to Enable
R/W Hold Time After Enable
Address Input Valid to
Address Output Delay
Conditions
(Note 3)
(Note 3)
(Note 3)
(Note 5)
(Note 2)
(Note 1)
(Note 1)
(Note 1)
(Note 4)
-90
Min Max
22
7
8
90
90
35
-12
Turbo
Min Max Off Unit
24
ns
9
ns
10
ns
120 Add 20** ns
120
ns
35
ns
45
48
ns
0
0
ns
36
40
ns
38
40
ns
38
42
ns
10
16
ns
0
0
ns
30
35
ns
NOTES: 1. RD timing has the same timing as DS and PSEN signals.
2. RD and PSEN have the same timing for 80C51.
3. Any input used to select an internal PSD4135G2V function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS signals.
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