ST72521M7TC 查看數據表（PDF） - STMicroelectronics

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ST72521M7TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521M/R/AR

12.12 10-BIT ADC CHARACTERISTICS

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ 1)

Max

fADC

VAREF

VAIN

IL

RAIN

CAIN

ADC clock frequency

Analog reference voltage 2)

Conversion voltage range 3)

Input leakage current

for analog input

External input impedance

External capacitor on analog input

fAIN Variation freq. of analog input signal

-40°C≤TA≤85°C range

Other TA ranges

0.4

0.7*VDD

VSSA

2

5.5

VAREF

±250

±1

see

Figure

110 and

Figure

1113)4)5)

CADC Internal sample and hold capacitor

12

tSTAB Stabilization time after ADC enable

0 5)

Conversion time (Sample+Hold)

fCPU=8MHz, SPEED=0

7.5

tADC - No of sample capacitor loading cycles fADC=2MHz

4

- No. of Hold conversion cycles

11

Unit

MHz

V

nA

µA

kΩ

pF

Hz

pF

µs

1/fADC

Figure 110. RAIN max. vs fADC with CAIN=0pF4)

45

40

35

2 MHz

30

1 MHz

25

20

15

10

5

0

0

10

30

70

CPARASITIC (pF)

Figure 112. Typical A/D Converter Application

Figure

111.

Recommended

CAIN

&

RAIN

5)

values.

1000

Cain 10 nF

100

Cain 22 nF

Cain 47 nF

10

1

0.1

0.01

0.1

1

10

fAIN(KHz)

VAIN

RAIN

AINx

CAIN

VDD

VT

0.6V

VT

0.6V

ST72XXX

2kΩ(max)

10-Bit A/D

Conversion

IL

±1µA

CADC

6pF

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-

lines and are not tested.

2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.

3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data

based on characterization results, not tested in production.

4. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-

pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

5. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization and to allow

the use of a larger serial resistor (RAIN).

184/199

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