PCA8538UG(2014) 查看數據表（PDF） - NXP Semiconductors.
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PCA8538UG Datasheet PDF : 107 Pages
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NXP Semiconductors
PCA8538
Automotive 102 x 9 Chip-On-Glass LCD segment driver
15.2.2 Device synchronization
The SYNC0 and SYNC1 lines are provided to maintain the correct synchronization
between all cascaded PCA8538. (SYNC1 must not be connected when using an
externally supplied VLCD.)This synchronization is guaranteed after the Power-On Reset
(POR). SYNC0 and SYNC1 are organized as input/output pins.
Both, the internally generated clock frequency or, alternatively, an externally supplied
clock signal can be used in cascaded applications.
In cascaded applications that use the internal clock, the master PCA8538 with device
address A[1:0] = 00 must have the OSC pin connected to VSS1 and the COE bit is set
logic 1, so that this device uses its internal clock to generate a clock signal at the CLK pin.
The other PCA8538 devices are having the OSC pin connected to VDD1, meaning that
these devices are ready to receive an external clock signal which is provided by the
master device with subaddress A[1:0] = 00.
If the master is providing the clock signal to the slave devices, care must be taken that the
sending of display enable or disable will be received by both, the master and the slaves at
the same time. When the display is disabled, the output from pin CLK is disabled too. The
disconnection of the clock may result in a DC component for the display.
In cascaded applications that use an external clock, all devices have the OSC pin
connected to VDD1 and thus an external CLK being provided for the system (all devices
connected to the same external CLK).
15.2.3 Display data
The storage of display data is determined by the contents of the device address register
(see Section 8.2.3 on page 10). Storage is allowed only when the content of the device
address register matches with the hardware device address applied to the pins A0 and
A1. If the content of the device address register and the hardware device address do not
match, data storage is inhibited but the data pointer is incremented as if data storage had
taken place. The hardware device address must not be changed while the device is being
accessed on the interface.
15.2.4 Data read
Only when the content of the device address register (see Section 8.2.3 on page 10)
matches with the hardware device address applied to the pins A0 and A1, the temperature
or device status readout (see Section 8.2.7 on page 12) is activated. If the content of the
device address register and the hardware device address do not match, the data output
pin (SDA or SDO) of the device is in 3-state. With this, bus conflicts and incorrect reading
is prevented.
PCA8538
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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