PCA8538UG(2014) 查看數據表（PDF） - NXP Semiconductors.
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PCA8538UG Datasheet PDF : 107 Pages
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NXP Semiconductors
PCA8538
Automotive 102 x 9 Chip-On-Glass LCD segment driver
9.2 I2C interface
The I2C-bus is selected by connecting pin IFS to VDD1.
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
In Chip-On-Glass (COG) applications, where the track resistance between the SDA
output pin to the system SDA input line can be significant, the bus pull-up resistor and the
Indium Tin Oxide (ITO) track resistance may generate a voltage divider. As a
consequence it may be possible that the acknowledge cycle, generated by the LCD driver,
cannot be interpreted as logic 0 by the master. Therefore it is an advantage for COG
applications to have the acknowledge output separated from the data line. For that
reason, the SDA line of the PCA8538 is split into SDI/SDAIN and SDAOUT.
In COG applications where the acknowledge cycle is required, it is necessary to minimize
the track resistance from the SDAOUT pin to the system SDI/SDAIN line to guarantee a
valid LOW level.
By splitting the SDA line into SDI/SDAIN and SDAOUT (having the SDAOUT open
circuit), the device could be used in a mode that ignores the acknowledge cycle.
Separating the acknowledge output from the serial data line can avoid design efforts to
generate a valid acknowledge level. However, in that case the I2C-bus master has to be
set up in such a way that it ignores the acknowledge cycle.2
By connecting pin SDAOUT to pin SDI/SDAIN the SDI/SDAIN line becomes fully I2C-bus
compatible. The following definition assumes SDI/SDAIN and SDAOUT are connected
and refers to the pair as SDA.
9.2.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as a control signal (see Figure 38).
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Fig 38. I2C-bus - bit transfer
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9.2.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START
condition (S).
2. For further information, consider the NXP application note: Ref. 1 “AN10170”.
PCA8538
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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